Index:    Integer Instructions
          Interger Arithmetic Instructions
          Interger Compare Instructions
          Integer Logical Instructions
          Integer Rotate Instructions
          Integer Shift Instructions
	  Integer Load Instructions
          Integer Store Instructions
          Integer Load and Store with Byte-Reverse Instructions
          Integer Load and Store Multiple Instructions
          Integer Load and Store String Instructions

          Floating-Point Instructions
          Floating-Point Arithmetic Instructions
          Floating-Point Multiply-Add Instructions
          Floating-Point Rounding and Conversion Instructions
          Floating-Point Compare Instructions
          Floating-Point Status and Control Register Instructions
          Floating-Point Move Instructtions
          Floating-Point Load Instructions
          Floating-Point Store Instructions

          Branch and Flow Control Instructions
          Branch Instructions
          Condition Register Logical Instructions

          Some Others :)
          Trap Instructions
          Move to/from Condition Register Intstructions
          Memory Synchronisation Instructions

          VEA Instructions
          Processor Control Instructions
          Memory Synchronisation Instructions
          User-Level Cache Instructions
          External Control Instructions

          OEA Instructions
          System Linkage Instructions
          Move to/from Machine State Register Instructions
          Move to/from Special-Purpose Register Instructions
          Memory Control Instructions
          System Linkage Instructions
          Segment Register Manipulation Instructions
          Translation lookaside Buffer Management Instructions


Integer Arithmetic Instructions
Mnemonic                              Unit                           Cycles

addi                                  Integer & SRU                  1
addis                                 Integer & SRU                  1
add (add. addo addo.)                 Integer & SRU                  1
subf (subf. subfo subfo.)             Integer                        1
addic                                 Integer                        1
addic.                                Integer                        1
subfic                                Integer                        1
addc (addc. addco addco.)             Integer                        1
subfc (subfc. subfco subfco.)         Integer                        1
adde (adde. addeo addeo.)             Integer                        1
subfe (subfe. subfeo subfeo.)         Integer                        1
addme (addme. addmeo addmeo.)         Integer                        1
subfme (subfme. subfmeo subfmeo)      Integer                        1
addze (addze. addzeo addzeo.)         Integer                        1
subfze (subfze subfzeo subfzeo.)      Integer                        1
neg (neg. nego nego.)                 Integer                        1
mulli                                 Integer                        2,3
mullw (mullw. mullwo mullwo.)         Integer                        2,3,4,5
mulhw (mulhw.)                        Integer                        2,3,4,5
mulhwu (mulhwu.)                      Integer                        2,3,4,5,6
divw (divw. divwo divwo.)             Integer                        37@
divwu (divwu. divwuo divwuo.)         Integer                        37@

@ Cycle for PPC 603e PID1 to PID6, for PID7 it's 20 cycles


Integer Compare Instructions
Mnemonic                              Unit                           Cycles

cmpi                                  Integer & SRU                  1#
cmp                                   Integer & SRU                  1#
cmpli                                 Integer & SRU                  1#
cmpl                                  Integer & SRU                  1#

Cycle times marked with # immediatly forward their CR results to the BPU for fast branch resolution


Integer Logical Instructions
Mnemonic                              Unit                           Cycles

andi.                                 Integer                        1
andis.                                Integer                        1
ori                                   Integer                        1
oris                                  Integer                        1
xori                                  Integer                        1
xoris                                 Integer                        1
and (and.)                            Integer                        1
or (or.)                              Integer                        1
xor (xor.)                            Integer                        1
nand (nand.)                          Integer                        1
nor (nor.)                            Integer                        1
eqv (eqv.)                            Integer                        1
andc (andc.)                          Integer                        1
orc (orc.)                            Integer                        1
extsb (extsb.)                        Integer                        1
extsh (extsh.)                        Integer                        1
cntlzw (cntlzw.)                      Integer                        1


Integer Rotate Instructions

Mnemonic                              Unit                           Cycles

rlwinm (rlwinm.)                      Integer                        1
rlwnm (rlwnm.)                        Integer                        1
rlwimi (rlwimi.)                      Integer                        1


Integer Shift Instructions

Mnemonic                              Unit                           Cycles

slw (slw.)                            Integer                        1
srw (srw.)                            Integer                        1
srawi (srawi.)                        Integer                        1
sraw (sraw.)                          Integer                        1


Integer Load Instructions

Mnemonic                              Unit                           Cycles

lbz                                   LSU                            2:1
lbzx                                  LSU                            2:1
lbzu                                  LSU                            2:1
lbzux                                 LSU                            2:1
lhz                                   LSU                            2:1
lhzx                                  LSU                            2:1
lhzu                                  LSU                            2:1
lhzux                                 LSU                            2:1
lha                                   LSU                            2:1
lhax                                  LSU                            2:1
lhau                                  LSU                            2:1
lhaux                                 LSU                            2:1
lwz                                   LSU                            2:1
lwzx                                  LSU                            2:1
lwzu                                  LSU                            2:1
lwzux                                 LSU                            2:1

Cycle times marked with : specify cycles of total latency and throughput for
 pipelined load and store instruction



Integer Store Instructions

Mnemonic                              Unit                           Cycles

stb                                   LSU                            2:1
stbx                                  LSU                            2:1
stbu                                  LSU                            2:1
stbux                                 LSU                            2:1
sth                                   LSU                            2:1
sthx                                  LSU                            2:1
sthu                                  LSU                            2:1
sthux                                 LSU                            2:1
stw                                   LSU                            2:1
stwx                                  LSU                            2:1
stwu                                  LSU                            2:1
stwux                                 LSU                            2:1

Cycle times marked with : specify cycles of total latency and throughput for
 pipelined load and store instruction



Integer Load and Store with Byte-Reverse Instructions

Mnemonic                              Unit                           Cycles

lhbrx                                 LSU                            2:1
lwbrx                                 LSU                            2:1
sthbrx                                LSU                            2:1
stwbrx                                LSU                            2:1

Cycle times marked with : specify cycles of total latency and throughput for
 pipelined load and store instruction



Integer Load and Store Multiple Instructions

Mnemonic                              Unit                           Cycles

lmw                                   LSU                            2+n&
stmw                                  LSU                            1+n&

Cycle times marked with & require a variable number of cycle due to serialization
Load and store multiple instruction cycles are shown as a fixednumber of cycles
 plus a variable number of cyles where 'n' is the number of words accessed by the
 instruction



Integer Load and Store String Instructions

Mnemonic                              Unit                           Cycles

lswi                                  LSU                            2+n&
lswx                                  LSU                            2+n&
stswi                                 LSU                            1+n&
stswx                                 LSU                            1+n&

Cycle times marked with & require a variable number of cycle due to serialization
Load and store multiple instruction cycles are shown as a fixednumber of cycles
 plus a variable number of cyles where 'n' is the number of words accessed by the
 instruction



Floating Point Arithmetic Instructions

Mnemonic                              Unit                           Cycles

fadd (fadd.)                          FPU
fadds (fadds.)                        FPU                            1-1-1@
fsub (fsub.)                          FPU                            1-1-1@
fsubs (fsubs.)                        FPU                            1-1-1@
fmul (fmul.)                          FPU                            2-1-1@
fmuls (fmuls.)                        FPU                            1-1-1@
fdiv (fdiv.)                          FPU                            33@
fdivs (fdivs.)                        FPU                            18@
fres (fres.)                          FPU                            18@
frsqrte (frsqte.)                     FPU                            1-1-1@
fsel (fsel.)                          FPU                            1-1-1@

Cycle times marked with @ immediatly forward their CR result to the BPU for fast branch
resolution

Cycle times marked with a - specify the number of clock cycles in each pipeline stage.
Instruction with single entry in the cycles column are not pipelined.



Floating Point Multiply-Add Instructions

Mnemonic                              Unit                           Cycles

fmadd (fmadd.)                        FPU                            2-1-1@
fmadds (fmadds.)                      FPU                            1-1-1@
fmsub (fmsub.)                        FPU                            2-1-1@
fmsubs (fmsubs.)                      FPU                            1-1-1@
fnmadd (fnmadd.)                      FPU                            2-1-1@
fnmadds (fnmadds.)                    FPU                            1-1-1@
fnmsub (fnmsub.)                      FPU                            2-1-1@
fnmsubs (fnmsubs.)                    FPU                            1-1-1@

Cycle times marked with @ immediatly forward their CR result to the BPU for fast branch
resolution

Cycle times marked with a - specify the number of clock cycles in each pipeline stage.
Instruction with single entry in the cycles column are not pipelined.



Floating Point Rounding and Conversion Instructions

Mnemonic                              Unit                           Cycles

frsp (frsp.)                          FPU                            1-1-1@
fctiw (fctiw.)                        FPU                            1-1-1@
fctiwz (fctiwz.)                      FPU                            1-1-1@

Cycle times marked with @ immediatly forward their CR result to the BPU for fast branch
resolution

Cycle times marked with a - specify the number of clock cycles in each pipeline stage.
Instruction with single entry in the cycles column are not pipelined.



Floating Point Compare Instructions

Mnemonic                              Unit                           Cycles

fcmpu                                 FPU                            1-1-1@
fcmpo                                 FPU                            1-1-1@

Cycle times marked with @ immediatly forward their CR result to the BPU for fast branch
resolution

Cycle times marked with a - specify the number of clock cycles in each pipeline stage.
Instruction with single entry in the cycles column are not pipelined.



Floating Point Status and Control Register Instructions

Mnemonic                              Unit                           Cycles

mffs (mffs.)                          FPU                            1-1-1&@
mcrfs                                 FPU                            1-1-1&
mtfsfi (mtfsfi.)                      FPU                            1-1-1&@
mtfsf (mtfsf.)                        FPU                            1-1-1&@
mtfsb0 (mtfsb0.)                      FPU                            1-1-1&@
mtfsb1 (mtfsb1.)                      FPU                            1-1-1&@

Cycle times marked with @ immediatly forward their CR result to the BPU for fast branch
resolution

Cycle times marked with a - specify the number of clock cycles in each pipeline stage.
Instruction with single entry in the cycles column are not pipelined.

Cycle times marked with & require a variable number of cycle due to serialization



Floating Point Move Instructions

Mnemonic                              Unit                           Cycles

fmr (fmr.)                            FPU                            1-1-1@
fneg (fneg.)                          FPU                            1-1-1@
fabs (fabs.)                          FPU                            1-1-1@
fnabs (fnabs.)                        FPU                            1-1-1@

Cycle times marked with @ immediatly forward their CR result to the BPU for fast branch
resolution

Cycle times marked with a - specify the number of clock cycles in each pipeline stage.
Instruction with single entry in the cycles column are not pipelined.



Floating-Point Load Instructions

Mnemonic                              Unit                           Cycles

lfs                                   LSU                            2:1
lfsx                                  LSU                            2:1
lfsu                                  LSU                            2:1
lfsux                                 LSU                            2:1
lfd                                   LSU                            2:1
lfdx                                  LSU                            2:1
lfdu                                  LSU                            2:1
lfdux                                 LSU                            2:1

Cycle times marked with : specify cycles of total latency and throughput for
 pipelined load and store instruction



Floating-Point Store Instructions

Mnemonic                              Unit                           Cycles

stfs                                  LSU                            2:1
stfsx                                 LSU                            2:1
stfsu                                 LSU                            2:1
stfsux                                LSU                            2:1
stfd                                  LSU                            2:1
stfdx                                 LSU                            2:1
stfdu                                 LSU                            2:1
stfdux                                LSU                            2:1
stfiwx                                LSU                            2:1

Cycle times marked with : specify cycles of total latency and throughput for
 pipelined load and store instruction



Branch Instructions

Mnemonic                              Unit                           Cycles

b (ba bl bla)                         BPU                            1*
bc (bca bcl bcla)                     BPU                            1*
bclr (bclrl)                          BPU                            1*
bcctr (bcctrl)                        BPU                            1*

* These operations may be folded for an effective cycle time of 0



Condition Register Logical Instructions

Mnemonic                              Unit                           Cycles

crand                                 SRU                            1
cror                                  SRU                            1
crxor                                 SRU                            1
crnand                                SRU                            1
crnor                                 SRU                            1
creqv                                 SRU                            1
crandc                                SRU                            1
crorc                                 SRU                            1
mcrf                                  SRU                            1



Trap Instructions

Mnemonic                              Unit                           Cycles

twi                                   Integer                        2
tw                                    Integer                        2



Move to/from Condition Register Instructions

Mnemonic                              Unit                           Cycles

mtcrf                                 SRU                            1
mcrxr                                 SRU                            1&
mfcr                                  SRU                            1

Cycle times marked with & require a variable number of cycle due to serialization



Memory Synchronisation Instructions (UISA)

Mnemonic                              Unit                           Cycles

lwarx                                 LSU                            2:1
stwcx.                                LSU                            8
sync                                  SRU                            1&

Cycle times marked with & require a variable number of cycles due to serialisation
Cycle times marked with : specify cycles of total latency and throughput for
 pipelined load and store instruction



Processor Control Instructions (VEA)

Mnemonic                              Unit                           Cycles

mftb                                  SRU                            1
mttb                                  SRU                            1



Memory Synchronization Instructions (VEA)

Mnemonic                              Unit                           Cycles

eieio                                 SRU                            1
isync                                 SRU                            1&

Cycle times marked with & require a variable number of cycles due to serialisation



User-Level Cache Instructions (VEA)

Mnemonic                              Unit                           Cycles

dcbt                                  LSU                            2
dcbtst                                LSU                            2
dcbz                                  LSU                            10&
dcbst                                 LSU                            2/5&
dcbf                                  LSU                            2/5&
Icbi                                  LSU                            3&

Cycle times marked with & require a variable number of cycles due to serialisation
Cycle times marked with / specify hit and miss times for cache management instructions
 that require conditional bus activity



External Control Instructions (VEA)

Mnemonic                              Unit                           Cycles

eciwx                                 LSU                            2:1
ecowx                                 LSU                            2:1

Cycle times marked with : specify cycles of total latency and throughput for
 pipelined load and store instruction



System Linkage Instructions (OEA)

Mnemonic                              Unit                           Cycles

sc                                    SRU                            3
rfi                                   SRU                            3



Move to/from Machine State Register Instructions (OEA)

Mnemonic                              Unit                           Cycles

mtmsr                                 SRU                            2
mfmsr                                 SRU                            1



Move to/from Special-Purpose Register Instructions (OEA)

Mnemonic                              Unit                           Cycles

mtspr (not IBATs)                     SRU                            2(XER-&)
mtspr (IBATs)                         SRU                            2&
mfspr (DBATs)                         SRU                            3&
mfspr (IBATs)                         SRU                            3&

Cycle times marked with & require a variable number of cycle due to serialization



Memory Control Instructions (OEA)

Mnemonic                              Unit                           Cycles

dcbi                                  LSU                            2&

Cycle times marked with & require a variable number of cycle due to serialization



Segment Register Manipulation Instructions (OEA)

Mnemonic                              Unit                           Cycles

mtsr                                  SRU                            2
mtsrin                                SRU                            2
mfsr                                  SRU                            3&
mfsrin                                SRU                            3&

Cycle times marked with & require a variable number of cycle due to serialization



Translation Lookaside Buffer Management Instructions (OEA)

Mnemonic                              Unit                           Cycles

tlbie                                 LSU                            3&
tlbsync                               LSU                            2&
tlbld                                 LSU                            2&
tlbli                                 LSU                            3&

Cycle times marked with & require a variable number of cycle due to serialization